
Staff Engineer, Design Verification
- Assago, Milano Milano
- Tempo indeterminato
- Full time
- Read and understand Digital designs in RTL (Verilog)
- Read and understand transistor level designs of circuits (Schematics)
- Work with the design team to understand the design intent and bring up the verification plan and schedule
- Develop Real-Number models (Verilog-AMS/SV-AMS) to reproduce analog circuits behavior
- Create test benches and tests for specific mixed-signal products
- Improve verification flow for broad use across products and quick reuse on new products
- Complete verification of complex projects on schedule and coordinate the verification activity
- Cooperate with cross-functional teams and coordinate priorities to achieve higher productivity
- Follow-up with project team members, to ensure customer satisfaction and gather feedback during and after projects are complete
- Deep Knowledge of SystemVerilog (IEEE 1800)
- Experienced with UVM (Universal Verification Methodology) (IEEE 1800.2-2020)
- Scripting and design automation (TCL, PERL, RUBY, SHELL)
- Implementing mixed signal digital design verification methodologies and flows
- Modeling of analog (Real Number Models) in Verilog-AMS and SystemVerilog
- Experience with Cadence based Verification tools: Virtuoso, Simvision, Xcelium, vManager
- Verification Planning and developing verification plan
- Architecting and building test benches and environments
- Intuitive and analytical understanding of transistor-level circuit design
- Knowledge of PSL / SVA Assertions is a plus
- Formal Verification is a plus
- Previous experience with I2C, PMIC or USB-C is a plus
- Fluent in English